This indicates data sample time t d trails optimum sample time t O , and thus, the phase of sampling signal correspondingly lags the phase of serial data signal Exemplary Timing Recovery Method []. At a first step [] , phase interpolator receives the reference signals having different phases in reference signal set Interpolator combines in varying relative proportions the reference signals into data sampling signal in response to the plurality of digital phase control signals , thereby producing data sampling signal with a digitally controlled interpolated phase.
Phase interpolator also produces phase sampling signal in response to the digital phase control signal such that the phase sampling signal and the data sampling signal are offset in phase from one another by a predetermined amount corresponding to a fraction for example, one-half of a symbol period of serial data signal At a next step [] , data path samples serial data signal i. Phase path also samples serial data signal at phase sample times t p offset in phase relative to the data sample times t d to produce phase samples in phase signal At a next step [] depicted in dotted line in FIG.
Next steps , and described below collectively represent step At step , phase detector examines the data samples in data signal to detect occurrences of low-to-high and high-to-low data sample transitions. Such transitions occur at symbol boundaries. At next step [] , phase detector determines whether each of the data sample times t d near to detected data sample transitions from step is early or late with respect to optimum symbol sample time t O , based on data and phase samples near the detected data sample transitions.
At next step [] , phase detector derives phase error signal indicative of whether each data sample time t d is early or late with respect to the optimum symbol sample time t O. Phase detector derives as the phase error signal an Early decision signal indicating the phase of sampling signal leads the phase of serial data signal when the data sample time t d precedes optimum sample time t O. Therefore, phase detector produces a series of such Early decision signals over time while the phase of sampling signal leads the phase of serial data signal Alternatively, phase detector [] derives as the phase error signal a Late decision signal indicating the phase of sampling signal lags the phase of serial data signal when the data sample time t d follows optimum sample time t O.
Therefore, phase detector produces a series of such Late decision signals over time while the phase of sampling signal lags the phase of serial data signal On the other hand, phase detector [] tends to produce a series of randomly alternating Late and Early decision signals over time while sampling signal and serial data signal are phase aligned with each other.
At a next step [] , phase error processor processes the phase error over time i. The set of phase control commands includes a phase-hold command, a phase-retard command, and a phase-advance command. Phase error processor asserts:. Alternatively, signal rotator holds the plurality of digital phase control signals in position, thereby preventing rotation of the phase control signals and correspondingly the interpolated phase of data sampling signal , in response to the phase-hold control command when asserted by phase error processor A step is initiated in response to the phase retard command.
At step , the interpolated phase of sampling signal is retarded relative to serial data signal A step [] is initiated in response to the phase advance command. At step , the interpolated phase of sampling signal is advanced relative to serial data signal A step [] is initiated in response to the phase hold command. At step , the interpolated phase of sampling signal is held at a present value.
As described above with reference to FIG. These sampling signals are generated by interpolation techniques performed by phase interpolator These interpolation techniques can provide sampling signal phases that span a complete rotation of degrees. These phases are achieved without the use of conventional techniques, such as time-delays. In addition to the exemplary timing recovery and receiver applications described herein, the phase interpolation techniques of the present invention may be used in other applications.
An exemplary phase interpolator environment is now described. Environment includes a phase interpolator , such as phase interpolator , and a stage controller , such as phase control signal rotator or other controller. The controller is not limited to a control signal rotator. Interpolator [] includes a plurality of reference stages a - d that are each coupled to stage controller , and a combining node that is coupled to each of reference stages As shown in FIG.
These reference signals are each periodic waveforms that each have a distinct phase. Examples of periodic waveforms include sinusoid, rectangular waveforms, trapezoidal waveforms, and other similar periodic signals. In addition, each reference stage [] receives a corresponding control signal from stage controller Each reference stage [] generates a component signal from its corresponding reference signal according to a scaling factor that is the ratio of a component signal magnitude to its corresponding reference signal magnitude.
A reference stage scaling factor is determined by its corresponding control signal For example, reference stage a generates component signal a from reference signal a according to a scaling factor determined by control signal a. These scaling factors control the magnitude of corresponding component signals [] This controlled magnitude may be zero.
Thus, control signals may scale as well as activate and deactivate corresponding component signals Component signals [] are each sent to combining node Combining node [] combines each of component signals to produce an output signal This combining includes summing each of the individual component signals some of which may have a magnitude equal to zero.
As a result of this combining, output signal is a periodic waveform having a phase that is derived from the phases of component signals This derivation is referred to herein as phase interpolation. Stage controller [] generates stage control signals in response to an interpolation command that is received from a master system controller not shown , such as rotator control commands received from phase error processor Exemplary details regarding interpolation command are provided in greater detail below.
As described above, each reference stage [] generates a component signal from a reference signal having a distinct phase. These generated component signals each have a distinct phase that is determined by the corresponding reference signal phase. For example, a component signal may have the same or substantially the same phase as its corresponding reference signal Alternatively, a component signal may have a phase that is offset by a predetermined phase shift from the corresponding reference signal phase.
Through phase interpolation, the present invention can provide a complete range of phases i. This complete range is provided through the deployment of more than two reference stages and a strategic predetermined selection of reference signal phases.
This implementation includes four reference stages a - d that receive reference signals a - d , respectively. Each of reference signals a - d has a distinct, predetermined phase. Thus, the implementation of FIG. In addition, FIG. Each conversion module receives and converts a reference signal into a corresponding component signal according to a scaling factor.
Scaling module establishes this scaling factor in response to its corresponding control signal Details regarding implementations of scaling module and conversion module are provided below. The phase interpolator [] implementation shown in FIG.
Accordingly, FIG. This implementation is capable of generating output signal having one of eight possible phases. These eight possible phases are spaced at intervals of 45 degrees, and span a complete rotation of degrees. Phasor diagram includes phasors , , , and These phasors have the same phases as reference signal phases a , b , c , and d , respectively. In addition, phasor diagram [] includes phasors , , , and These phasors have phases that are between reference phases a - d.
Table 1, below, shows how the values of control signals [] a through d determine which of the phasors in FIG. Thus, the phase interpolator [] implementation of FIG. Thus, this circuit may be employed in the phase interpolator implementation of FIG. In this circuit, reference signals and component signals are each differential signal pairs that have an in-phase signal and a degrees out-of-phase signal.
Except for a degrees phase shift, these signals are the same. Similarly, component signal includes an in-phase signal and an out-of-phase signal These signals are time varying voltage signals. However, conversion module may employ other transconductance devices. Scaling module [] includes a current digital to analog converter IDAC that is coupled to the source terminals of FETs and, Scaling module [] receives binary control signal When binary control signal has a value of 1, IDAC operates as a current generator that enables a current to flow through the drain and source terminals of FETs and However, when binary control signal has a value of 0, IDAC does not enable current to flow i.
The flow of current [] enables reference signal to be converted into corresponding component signal That is, source current enables the conversion of differential reference signals and into differential component signals and , respectively. This conversion is performed according to a specific scaling factor.
Differential component signals [] and are electrical current signals that are combined at combining node with differential component signals from other reference stages This combining generates output signal An exemplary combining node circuit schematic is described below with reference to FIG.
As described above, the phase interpolator [] implementation of FIG. However, the present invention may achieve finer phase granularity through implementations where each control signal is capable of having more than two distinct values. This implementation enables output signal to have a greater number of phases than the implementation of FIG.
The FIG. Unlike reference stages [] of FIG. In particular, the implementation of FIG. However, any number may be employed. Scaling modules [] a - d each receive a respective one of subsignals a - d. These individual contributions are based on the value of the corresponding control subsignal As described above, scaling factor is the ratio of a component signal magnitude to its corresponding reference signal magnitude.
One of these scaling factors may be equal to zero, thereby causing corresponding component signal a to also have a magnitude of zero. Thus, the phase interpolator implementation of FIG. These five different magnitudes advantageously provide a number of attainable control signal phases across a degrees range that is greater than the eight phases achievable with the phase interpolator implementation of FIG.
Conversion modules includes two N channel metal oxide semiconductor NMOS field effect transistors FETs and that each have drain, source, and gate terminals. However, conversion modules may employ other transconductance devices. Each of IDACs [] a - d receives a respective one of binary control subsignals a - d and, enables a corresponding current to flow from the source terminals of FETs and when the respective control subsignal has a value of 1.
For example, IDAC a enables a current a to flow when subsignal a equals 1. However, when a control subsignal has a value of 0, the corresponding IDAC does not enable corresponding current to flow i. Currents [] a - d each contribute to an aggregate current The value of aggregate current depends on the number of IDACs that are receiving a subsignal having a value of 1.
As aggregate current increases, so does the scaling factor associated with the conversion of differential reference signals and into differential component signals and , respectively. Component signals [] and are electrical current signals. These current signals are combined at combining node with component signals from other reference stages An exemplary combining node circuit schematic is described below with reference to FIGS.
However, FIG. The combining node [] circuit of FIGS. Resistors and are each coupled to a voltage node , such as a Vdd rail. In addition, resistors and are coupled to reference stages a - d. As shown in FIGS. Similarly, resistor is coupled to a FET within each reference stage Output nodes and provide output signal in the form of a differential signal having an in-phase output signal and an out-of-phase output signal Output signals and are voltage signals measured in relation to a reference voltage, such as ground.
As described above with reference to FIGS. Examples of such electrical current signals include signals and , and signals and In the FIG. Similarly, in the FIG. In FIGS. Phase Rotation []. For exemplary purposes, the embodiment of phase interpolator depicted in FIG.
Also, the embodiment of control signal rotator depicted in FIG. Other embodiments of phase interpolator and correspondingly, of control signal rotator are possible, as would be apparent to one of ordinary skill in the relevant art s after reading the description provided herein. For example, phase interpolator can be implemented in accordance with the phase interpolator embodiments described above in connection with FIGS.
Phase control signal rotator [] also referred to as signal rotator receives phase control command set from phase error processor As mentioned above, and as depicted in FIG. Phase-advance command a can be considered as a rotate-left command that is, as a command to rotate the phase of sampling signal in a counter-clockwise direction to advance its phase. Phase-retard command a can be considered as a rotate-right command that is, as a command to rotate the phase of sampling signal in a clockwise direction to retard its phase.
Signal rotator [] manipulates the digital phase control signals in accordance with an asserted one of phase control commands , and provides the so manipulated digital phase control signals to phase interpolator , as will be described in further detail below. Signal rotator includes a plurality of storage cells arranged in a ring configuration, generally referred to as a ring of storage cells The ring of storage cells includes a plurality of ring segments a , b , c , and d connected to one another by signal lines a - d in the ring configuration, as depicted in FIG.
Each of the ring segments includes a plurality of the individual storage cells Each of the storage cells stores a corresponding one of the plurality of digital phase control signals In one arrangement, the ring of storage cells is implemented as a circular shift register responsive to a shift-left, a shift-right, and a shift-enable control input corresponding to commands a , b , and c , for example.
Each one of the digital phase control signals [] can be a digital i. An exemplary arrangement of digital phase control signals stored in ring is depicted in FIG. In the arrangement described above, digital phase control signals [] are divided among a plurality of digital phase control signal sets a , b , c , and d. Each of the signal sets a - d corresponds to a respective one of ring segments a , b , c , and d. In other words, the storage cells included in ring segment a collectively provide digital phase control signal set a to phase interpolator , and so on.
Phase interpolation is described above in connection with FIGS. Phase interpolator is capable of bringing about phase shifts having granularity that is finer than 45 degrees. These phase control signal sets are discrete signals capable of having more than two distinct values. Phase interpolator [] also receives reference signal set in FIG. Reference signal set includes reference signals a , b , c , and d. Therefore, phase interpolator [] can be considered as combining the signals in reference signal set , having the different phases, into sampling signal having the interpolated phase.
Phase interpolator varies the relative proportions of the reference signals so combined in response to the plurality of digital phase control signal applied to the interpolator.
More specifically, each of signal sets a - d controls the relative proportion of the corresponding one of the reference signals a - d combined into sampling signal by interpolator When phase error processor [] asserts rotate-left command a that is, the phase-advance command , signal rotator ring concurrently shifts-left that is, in the direction indicated by an arrow L each one of the digital phase control signals from a present storage element to an adjacent next storage element to the left of the present storage element, in response to the command.
Therefore, ring rotates all of the digital phase control signals in counter-clockwise direction L. In response, phase interpolator correspondingly rotates the interpolated phase of sampling signal in the counter-clockwise direction in a direction of decreasing phase , thereby advancing the phase of sampling signal relative to serial data signal When phase error processor [] asserts rotate-right command b that is, the phase-retard command , ring concurrently shifts-right that is, in a clockwise direction indicated by an arrow R each one of the digital phase control signals from the present storage element to an adjacent next storage element to the right of the present storage element, in response to the command.
Therefore, ring rotates all of the digital phase control signals in clockwise direction R. In response, phase interpolator correspondingly rotates the interpolated phase of sampling signal in the clockwise direction in a direction of increasing phase , thereby retarding the phase of sampling signal relative to serial data signal Phase-hold command [] c overrides either of commands a and b.
Therefore, when phase error processor asserts phase-hold command c , ring holds all of the digital control signals in each present storage element, in response to the command. In other words, phase-hold command c prevents all of the digital phase control signals and correspondingly the interpolated phase of sampling signal from rotating.
Phase-advance and -retard commands [] a and b can be implemented as pulsed commands. As such, a single, pulsed phase-advance command a also referred to as a phase-advance pulse a causes an incremental shift-left of one position, and correspondingly, an incremental phase advance, as described above.
Similarly, a single, pulsed phase-retard command b causes an incremental shift-right of one position, and correspondingly, an incremental phase retardation, as is also described above.
The rate at which the interpolated phase of sampling signal rotates corresponds to the repetition rate of pulsed phase-retard and phase-advance commands b and a. Shift register includes linearly arranged storage cells linked together to collectively form the ring configuration. Shift register includes left and right end cells not labeled , and a signal line coupling the end cells together.
Array includes storage cells arranged as a matrix of rows and columns, as depicted in FIG. Alternative implementations of ring are possible, as would be apparent to one of ordinary skill in the relevant art after reading the description provided herein.
Phasor Diagrams []. Each of the phase segments a - d is divided into individual, contiguous phase cells , each representative of a discrete phase value. The distribution of digital phase control signals within phase cells [] illustrated in FIG. As depicted in FIG. The consecutive phase-retard pulses b are represented as consecutive clockwise pointing arrows b in FIG. In accordance with the distribution of control signals depicted in FIG. The consecutive phase-advance pulses a are represented as consecutive counter-clockwise pointing arrows a in FIG.
In the exemplary configurations depicted in FIGS. For example, with reference to the exemplary circuits shown in FIGS. This, in turn, provides constant amplitude output signals Frequency Synchronization []. In the embodiment of interpolator described above in connection with FIG. Timing recover system includes phase interpolator coupled to a controller for controlling the phase interpolator. Controller includes data and phase paths and , phase detector , phase error processor , and phase control signal rotator Controller applies control signals to phase interpolator to control the interpolated phase of sampling signal and Controller includes phase error processor to derive an estimate of a frequency effort between sampling signal and serial data signal , as will be described in further detail below.
Controller manipulates control signals in response to the frequency offset, to cause phase interpolator to rotate the interpolated phase of sampling signal at a rate corresponding the frequency offset, so as to reduce the frequency offset between serial data signal and sampling signal Phase error processor includes a short-term phase error processor , a frequency offset estimator also referred to as a long-term phase processor , and a rotate command generator Short-term processor and frequency offset estimator receive phase error from phase detector Short-term processor [] integrates phase errors over a relatively short time period, and thus responds relatively rapidly to changes in phase between sampling signal and serial data signal Processor derives a phase adjust signal in response to the aforementioned short-term phase changes.
Processor provides the phase adjust signal to rotate command generator On the other hand, frequency estimator [] integrates phase errors over a relatively long period of time for example, in comparison to short-term processor , and thus, responds relatively slowly to changes in phase between sampling signal and serial data signal In alternative arrangements, the functions performed by frequency estimator [] and short-term processor can be combined into a single logic block.
Alternatively, frequency estimator can integrate signal output by short-term processor , to produce signal Also, short-term processor and frequency estimator can be implemented as accumulators, such that signals and include accumulator over- and under-flow conditions.
Other embodiments of phase error processor are possible as would be apparent to one of ordinary skill in the relevant art s , after reading the description provided herein. Rotate command generator [] derives rotate commands described above based on phase adjust signal and frequency offset estimate signal Rotate command generator can be part of one or both of blocks and In one embodiment, rotate command generator generates pulsed phase-advance and phase-retard commands a and b described above in response to signals and On the other hand, phase adjust signal tends to perturbate the above mentioned repetition rate and correspondingly the phase rotation rate of sampling signal , in response to short-term phase errors.
Other embodiments of rotate command generator [] are possible as would be apparent to one of ordinary skill in the relevant art s , after reading the description provided herein. Timing recovery module [] implements a phase and frequency locked that is, tracking loop, including phase controller , phase control signal rotator , and phase interpolator , all described previously.
The phase and frequency locked loop causes the sampling signal phase and frequency to track the serial data signal phase and frequency, whereby sampling signal and serial data signal remain phase-aligned and frequency synchronized over time. Short-term phase error processor for example, short-term filter [] in phase error processor establishes a phase tracking bandwidth of the phase and frequency locked loop. Long-term phase processor for example, filter establishes a frequency tracking bandwidth of the phase and frequency locked loop.
Short-term filter responds more quickly to phase changes in serial data signal than does long-term filter As a result, short-term absences of serial data signal caused by signal drop-outs and the like, for example can cause the phase and frequency locked loop to loose track of the serial data signal phase, since short-term filter is responsive to such short-term signal losses.
Therefore, after such signal losses, the phase and frequency locked loop must re-acquire the serial data signal phase so as to re-establish a phase locked condition. On the other hand, such short-term signal absences have less of an adverse affect on long-term filter [] Therefore, once the phase and frequency locked loop begins rotating the sampling signal phase at an initial rate to frequency synchronize the sampling and serial data signals and , the phase and frequency locked loop tends to continue rotating the sampling signal phase at the same initial rate during the short-term signal losses.
Therefore, when serial data signal returns after such a signal loss, sampling signal tends to still be frequency synchronized with serial data signal assuming the serial data signal frequency does not change substantially during the signal loss.
Thus, the phase and frequency locked loop need only re-establish the phase locked condition mentioned above, since the loop is still frequency synchronized with serial data signal This advantageously reduces the time required to re-acquire the phase locked condition.
Method [] expands on steps and of method described above in connection with FIG. Step includes steps , , and At step , short-term phase error processor derives short-term phase adjust signal by, for example, short-term filtering phase error signal Frequency estimator derives the frequency offset estimate by, for example, long-term filtering of phase error Next step [] includes a step For example, with reference again to example phase ring of FIG.
On the other hand, a step [] is initiated when the frequency of sampling signal is less than the frequency of serial data signal i. Example timing recovery systems [] and include control signal rotator for rotating phase control signals , and correspondingly, the interpolated phase of sampling signals and However, the present invention is not limited to such embodiments.
For example, FIG. A next step [] includes rotating the interpolated phase of sampling signal at a rate corresponding to the frequency offset, so as to reduce the frequency offset. High-speed Serial Transceiver []. Communication device is a multiple channel that is, multi-channel transceiver, including multiple receivers and multiple transmitters, as described below.
Each of the serial data signals is associated with a different channel. Communication device receives multiple analog serial data signals a , b , c , and d collectively referred to as multiple serial data signals Each of receive-lanes receives a corresponding one of multiple serial data signals , as depicted in FIG.
Each of receive-lanes processes the corresponding one of serial data signals to produce a corresponding one of multiple digital data streams a , b , c , and d collectively referred to as digital data streams Receive-lanes provide data streams to a digital data sample processor Communication device is referred to as a multiple receiver or multi-channel communication device because of the multiple receive-lanes and associated circuits, described below. Communication device [] includes a master timing generator for generating a master timing signal Master timing generator provides master timing signal to each of the multiple receive-lanes Communication device [] also includes multiple transmit-lanes a , b , c , and d collectively referred to as multiple transmit-lanes Data sample processor provides multiple transmit data streams a , b , c , and d collectively referred to as multiple transmit digital data streams to corresponding ones of transmit-lanes , as depicted in FIG.
Master timing generator provides master timing signal to each of the multiple transmit-lanes Transmit-lanes each transmit a corresponding one of multiple analog serial data signals a , b , c , and d collectively referred to as multiple transmit analog serial data signals In alternative embodiments, communication device may include more or fewer receive-lanes and transmit-lanes In an embodiment, exemplary receive-lane a is substantially identical to the other receive-lanes b - d , therefore the following description of receive-lane a shall suffice for the others.
Receive-lane a includes a data module , a phase module , and a sampling signal generator As depicted, processor includes a data demultiplexer module a and an interpolator control module a , both corresponding to receive-lane a.
Processor provides interpolator phase control signals a , including a first phase control signal set a 1 and a second phase control signal set a 2 , to sampling signal generator Start the engine.
Being careful of moving parts such as belts, pulleys and the fan blade, shine the timing light down on the marker. The light will allow you to see the notch on the balancer lined up with the marker. If the notch is not lined up in the proper position, turn the distributor to move the notch to the proper position. Tighten the distributor hold-down clamp bolt and double-check the timing.
Disconnect the timing light. Reconnect any lines that were disconnected. Replace the air cleaner. Robert Bayly, based in Apple Valley, California, began writing in , his "how to" articles can be found on eHow.
With more than 15 years in the auto industry, Bayly has been an auto and diesel mechanic, service writer and parts manager. He received certificates from Pontiac parts system , Cat Diesel engine service , Saab and Fiat parts- warranty system.
Step 1 Park the vehicle on a level, paved surface and set the parking brake. Step 2 Remove the wingnut on the top of the air cleaner and remove the air cleaner. Step 3 Look at the crankshaft pulley. Step 4 Rotate the crankshaft with a ratchet and socket. Step 5 Hook up an inductive timing light to the engine. Analog RF interface circuit includes an analog RF transmitter and an RF receiver for transmitting and receiving signals to and from one or more antennae operating in a wireless communication channel.
MAC circuit [] includes digital logic interface , which interfaces with PHY circuit , and a microcontroller-based control system. The microcontroller-based control system includes microcontroller , which can be implemented by an embedded microprocessor e.
Software for microcontroller can be stored, for instance, in non-volatile memory , and loaded into RAM at run time. Data from MAC circuit includes fine timing information to be provided to precision timing generator , which also receives coarse timing information from code source The fine and coarse timing information received at precision timing generator is used to provide, as discussed below, a highly accurate and reliable timing signal for use with UWB signaling.
Pulses output from transmitter pulse generator are band-limited in band pass filter for transmission into the wireless channel. Band pass filter is an optional element provided for shaping the power spectrum of the output signal to be transmitted over antenna ; antenna can also provide such shaping in whole or in part.
One implementation of precision timing generator [] of FIG. Reference clock signal can be provided, for example, from a conventional crystal oscillator not shown. In addition to reference clock signal , coarse timing generator also receives input signals that convey coarse timing information from code source of FIG. From these signals, coarse timing generator generates timing events e. Coarse timing generator can be implemented, for example, by a circuit including a delay locked loop or a phase locked loop.
Interpolator , which receives fine-timing information from MAC circuit , as mentioned above, then interpolates between timing events to obtain highly precise timing signals at time points between any two of coarse timing events Timing signals are then used to generate precise timing pulses in pulse generator Each of clock signal pairs a - d e.
Further, a predetermined phase separate adjacent clock signal pairs e. For illustration purpose, FIG. However, the number of output clock signals is not so limited. In general, an N-stage delay locked loop, such as delay locked loop , provides 2N clock signals of the same frequency that are equally spaced in phase.
In FIG. In general, a selector has 2N ways to select two consecutive phase clock signals out of 2N clock signals that are equally spaced in phase. A low power implementation of delay locked loop , with carefully controlled propagation delays in the logic elements and the interconnect paths, can be achieved on an integrated circuit using simple geometrical scaling rules in CMOS technology.
The operations of interpolator are described in conjunction with the waveforms segments - shown in FIG. Low pass filters [] a and b each receive one of the two selected clock signals output from selector at terminals a and b , and integrate the corresponding voltage step at each rising or falling edge of each clock signal.
The integrated voltage waveforms at terminals a and b , which correspond to integrating the voltage steps of the rising edges of clock signals a and b , respectively, are shown in FIG. Similarly, the integrated voltage waveforms at terminals a and b , which correspond to integrating the voltage steps of the falling edges of clock signals a and b , respectively, are shown in FIG. The integrated waveforms at terminals a and b are amplified by VGA a and b.
In this embodiment, the gains in VGA a and b are proportional to the respective weights assigned to the phases of the clock signals at terminals a and b.
In one implementation, the weights are provided as two binary fractions that sum to a binary 1 i. The output voltages of VGA a and b are summed in summer Referring to FIG. Similarly, the summed voltage waveform for the falling edge transitions of the clock signals at terminals a and b is shown in FIG. As seen in FIG. The integrated waveform segment , corresponding to the rising edge transition of the clock signal at terminal b —which occurs at a fixed time i.
By comparing threshold value with the summed voltage at terminal i. Similarly, the falling edge can be precisely obtained at time t 4 , according to the weighted sum of integrated waveform segments and Thus, the resulting clock signal in output waveform has a high logic value between times t 1 and t 4. For use in a UWB communication application using pulse position modulation, design considerations relevant to the present invention include a trade-off between the resolution of coarse timing generator [] and interpolator For example, if each delay element of delay locked loop is nominally picoseconds ps , then the nominally frequency of delay locked loop would be MHz, with neighboring clock signals being offset in phase by ps.
Hence, the coarse timing resolution in coarse timing generator is nominally ps. If DAC receives a 3-bit input, eight uniformly spaced output levels can be provided to control variable gain amplifiers a and b , thus providing eight fine-timing steps In a UWB application, coarse timing input can be modulated according to a code to achieve, for example, spectral spreading and multiple access control, while the fine timing input may be modulated according to a desired message stream e.
Thus, the resolution partitioning between the coarse and fine timing circuits may take into consideration both integrated circuit design trade-offs e.
If it is desired to adjust the duty cycle of the resulting output waveform, two highly precise clock signals based on the same phase locked loop or delay locked loop can be obtained using two sets of clock signal selectors and interpolators.
Such a circuit is illustrated by circuit [] shown of FIG. Coarse timing selector a and interpolator a form one precision timing generator to generate a first clock signal at terminal a.
This first clock signal can be generated, for example, in the manner described above in conjunction with FIGS. Similarly, using independent coarse timing and fine timing information, a second clock signal is generated at terminal b using coarse timing selector b and interpolator b.
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